A dual-bit nonvolatile memory structure may include three transistors, a first floating gate transistor, a second floating gate transistor, and the other is a select gate transistor. The two floating gate transistors are formed over portions of a common channel region. The floating gates for the two floating gate transistors extend completely across all of the channel region in at least one direction between field isolation regions. The first floating gate transistor is connected to a first bit line, and the second floating gate transistor is connected to a second bit line.
The dual-bit memory structure may have problems related to read disturb. For example, the data in the second floating gate transistor is to be read. The first bit line is grounded and the second bit line at a potential of about one volt. The state of the bit is determined by a sense amplifier that is connected to the second bit line. The control gate of the first floating gate transistor and the select gate are placed at relatively high potentials (about five volts or higher), so that electrons may flow beneath the first floating gate and select gate. The control gate of the second floating gate transistor is grounded during the read operation. Electrons may be injected into the floating gate of the first floating gate transistor while the second floating gate transistor is read. In other words, electrons within the channel under the first floating gate transistor may be pulled into the floating gate by the high potential on the control gate of the first floating gate transistor. If the first floating gate transistor is programmed to have a threshold voltage -2 volts, the reading of the second floating gate transistor typically will increase the threshold voltage of the first floating gate transistor as electrons are injected into the floating gate of the first floating gate transistor. Data in the first floating gate transistor may not be determined by a sense amplifier because it is at a state between being programmed and erased, or the data may be inverted, in which case the data in the floating gate does not correspond to the data originally programmed into it. Data disturb problems in any type of memory cell are undesired.